Field of the Invention
The invention relates to a memory cell formed with a trench filled with conductive material that is connected to a selection transistor by a connection having a vertical insulation collar. The invention also relates to a wafer having at least one memory cell of the type described above, to a semiconductor component having at least one memory cell of the type described above, and to a method for fabricating an insulating collar for a memory cell.
Memory cells for dynamic random access memories (DRAM) are known, for example, from International Publication WO 01/17019. Such memory cells have a capacitor for storing charges.
In this case, a DRAM memory cell usually has a selection transistor connected to a capacitor. The transistor has two diffusion regions (source, drain) of a first charge type (e.g. n-doped), which are separated from one another by a channel of a second charge type (e.g. p-doped). By applying suitable voltages to the gate of the selection capacitor, it is possible to control the current flow between the source and the drain via the channel, i.e. the information stored as charge in the capacitor can be read in or out.
In these known memory cells there is a problem in that parasitic transistors are present outside the memory cell, and in the event of a breakdown, this can lead to a loss of charge in the capacitor. Moreover, there is the problem that there must be a sufficient dielectric strength in order to prevent a punch-through.
In order to prevent the parasitic transistor, it is known, for example, from U.S. Pat. No. 6,027,494 to use a vertical insulation collar in the region of the connection of the selection transistor up to the capacitor. In this case, the vertical insulation collar is formed, for example, by a thick oxide layer that insulates the channel of the selection capacitor from the filling of the connection (e.g. doped polysilicon or a metal compound). The vertical insulation collar must also have a certain length in order to ensure the dielectric strength, so that the potential present can be reduced over the length.
On account of these conditions, the vertical insulation collar is relatively thick, which is an obstacle to constructing memory cells having the desired high integration density. Thus, the physical conditions necessitate forming the vertical insulation collar with a thickness of 10 to 15 nm. As a result, such a vertical insulation collar cannot be used in memory cells of the sub-70 nm generation. Only 1F (i.e. 70 nm) would be available for the connection between selection transistor and capacitor, and 30 nm is required for the vertical insulation collars. The remaining 40 nm would be available for conducting current. This narrow cross section would bring about a high resistance, which would lead to slower write and read times.